DocumentCode :
2866851
Title :
Bipolar memory LSI chips for computers
Author :
Hotta, Abhilash ; Ogiue, K. ; Mitsusada, K. ; Hinai, M. ; Yamaguchi, Kazuhiro ; Inadachi, M.
Author_Institution :
Hitachi Computer Group, Tokyo, Japan
Volume :
XXII
fYear :
1979
fDate :
14-16 Feb. 1979
Firstpage :
98
Lastpage :
99
Abstract :
This paper will assess a 3072b RAM with 470 gates developed for dynamic address translation and cache control, and a standard 1K × 1b RAM with an access time of 5.5ns used for buffer storage.
Keywords :
Buffer storage; Circuits; High performance computing; Laboratories; Large scale integration; Logic arrays; Metallization; Power dissipation; Read-write memory; Schottky diodes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
Conference_Location :
Philadelphia, PA, USA
Type :
conf
DOI :
10.1109/ISSCC.1979.1155907
Filename :
1155907
Link To Document :
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