A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS

Author

Anderson, Timothy ; Bui, Duc ; Moharil, Shriram ; Narnur, Soujanya ; Rahman, Mujibur ; Lell, Anthony ; Biscondi, Eric ; Shrivastava, Ashish ; Dent, Peter ; Yan, Mingjian ; Mahmood, Hasan

Author_Institution

Commun. Infrastruct. - DSP Syst., Texas Instrum., Dallas, TX, USA

fYear

2011

fDate

25-27 July 2011

Firstpage

82

Lastpage

86

Abstract

A next generation VLIW DSP Central Processing Unit (CPU) which has an integrated fixed point and floating point Instruction Set Architecture (ISA) is presented. It is designed to meet a 1.5 GHz core clock frequency in a 40nm process with aggressive area and power goals. In this paper, the benchmarking process and benefits of newly defined instructions such as complex matrix multiply is explained. Also, the CPU data path is described in detail, highlighting several novel micro-architecture features. Finally, our design methodology as well as verification methodology to ensure functional correctness utilizing formal equivalent verification is described.

Keywords

CMOS integrated circuits; fixed point arithmetic; floating point arithmetic; formal verification; instruction sets; CMOS; ISA; clock frequency; complex matrix multiply; floating point instruction set architecture; formal equivalent verification; frequency 1.5 GHz; integrated fixed point instruction set architecture; micro-architecture; next generation VLIW DSP central processing unit; size 40 nm; Adders; Arrays; Benchmark testing; Central Processing Unit; Digital signal processing; Pipelines; Registers; Additions; CPU; Complex Matrix Multiply; DSP; Fixed Point; Floating Point; Formal Verification; Multiply; SIMD;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Arithmetic (ARITH), 2011 20th IEEE Symposium on

Conference_Location

Tubingen

ISSN

1063-6889

Print_ISBN

978-1-4244-9457-6

Type

conf

DOI

10.1109/ARITH.2011.20

Filename

5992112