• DocumentCode
    2866964
  • Title

    Bipolar circuit scaling

  • Author

    Solomon, Paul ; Tang, Dong

  • Author_Institution
    IBM Corp., Yorktown Heights, NY, USA
  • Volume
    XXII
  • fYear
    1979
  • fDate
    14-16 Feb. 1979
  • Firstpage
    86
  • Lastpage
    87
  • Abstract
    This presentation will cover scaling principles for bipolar logic circuits which involve coordinated shrinking of the transistor´s size, and increasing current densities and doping levels, while staying within the transistor´s physical limitations. Emitter-coupled logic will be cited as an example.
  • Keywords
    Capacitance; Capacitors; Current density; FETs; Logic circuits; Logic design; Resistors; Semiconductor device doping; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1979.1155913
  • Filename
    1155913
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2866964