2-in-1 total process integration in MERIE etch chamber for Cu dual damascene applications

Author

Wu, Robert ; Zhang, Luke ; Yang, Jack ; Tsui, Joshua ; Jiang, Anbei ; Sun, Jennifer ; Yuan, Jie ; Hsieh, Peter ; Hung, Raymond ; Ye, Yan ; Hsueh, Gary ; Shieh, Jyu-Horng ; Liu, Jen-cheng ; Tsai, Chia-shueng

fYear

2000

fDate

2000

Firstpage

278

Lastpage

280

Abstract

Advanced Cu-low K dual damascene becomes one of the most promising interconnection technologies for the new generation device back-end process. The keys for production-worthy solution lies in the integration of post main etch resist strip and nitride removal step without having process drift and particle generation. In this paper, we present a complete process integration to combine resist strip, chamber clean, nitride etch and ensure no residue left on the trenches and vias. Baseline performance, 1700 wafer cycling test, process window, mix-run and mix-mode test results will be discussed. The entire integration is being tested at customer site

Keywords

copper; integrated circuit interconnections; sputter etching; Cu; Cu-low K dual damascene interconnection technology; MERIE etch chamber; chamber clean; nitride etch; process integration; resist strip; wafer treatment; Dielectric materials; Etching; Plasma applications; Plasma density; Polymers; Radio frequency; Resists; Strips; Surface cleaning; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

0-7803-5921-6

Type

conf

DOI

10.1109/ASMC.2000.902601

Filename

902601