Tungsten silicide gate stack optimization for 170-nm DRAM technology

This paper discusses integration issues related to CVD WSi_x polycide process for 170-nm DRAM technology. Some problems encountered were: etch pits, sidewall protrusions, and electrical gate oxide thickness variations. The etch pits were eliminated by hardware and process modifications, to achieve a uniform W concentration in the as-deposited WSi_x film. Sidewall protrusions were eliminated by incorporating an RTA anneal prior to sidewall oxidation of the polycide stack. The variations in electrical gate oxide thickness are associated with high fluorine levels, and these were controlled by using a calibrated MFC for WF6 gas during the CVD WSi_x deposition