DocumentCode
2867231
Title
A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS
Author
Cho, Lan-Chou ; Lee, Chihun ; Liu, Shen-luan
Author_Institution
Nat. Taiwan Univ., Taipei
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
48
Lastpage
586
Abstract
A 33.6-to-33.8 Gb/s burst-mode CDR circuit is realized in 90nm CMOS technology. The LC gated VCO, the phase selector the input matching circuit, and the wideband data buffer are discussed. With 2n-1 PRBS input, the measured rms jitter for the recovered data is 1.15ps at 33.72Gb/s. This CDR can tolerate 31 consecutive identical bits with a locking time of 0.2ns (<7b interval). It consumes 73mW from a 1.2V supply excluding the buffers.
Keywords
CMOS integrated circuits; buffer circuits; jitter; optical communication equipment; synchronisation; voltage-controlled oscillators; 0.2 ns; 1.2 V; 33.6 to 33.8 Gbit/s; 73 mW; 90 nm; CMOS technology; burst mode; clock recovery; data buffer; data recovery; passive optical networks; phase selector; voltage controlled oscillators; Bandwidth; CMOS technology; Circuits; Clocks; Computer buffers; Delay; Impedance matching; Jitter; Passive optical networks; Phase locked loops;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0853-9
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373581
Filename
4242258
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