DocumentCode
2867258
Title
A 40mW 3.5kΩ 3Gb/s CMOS Differential Transimpedance Amplifier Using Negative-Impedance Compensation
Author
Tsai, Chia-Ming ; Chen, Wen-Tsao
Author_Institution
National Chiao Tung Univ., Hsinchu
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
52
Lastpage
586
Abstract
Combining the self-compensated topology with the negative-impedance-compensation technique, a differential TIA with enlarged input-capacitance tolerances is designed in a 0.18μm CMOS technology. The DR is measured to be >20dB without using any gain control. The complete TIA IC consumes 40mW from a 1.8V supply.
Keywords
CMOS integrated circuits; differential amplifiers; gain control; 0.18 micron; 1.8 V; 3 Gbit/s; 3.5 kohm; 40 mW; CMOS technology; differential transimpedance amplifier; gain control; negative-impedance compensation; CMOS technology; Differential amplifiers; Optical amplifiers; Optical buffering; Optical feedback; Optical receivers; Optical sensors; Optical transmitters; Stimulated emission; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0852-0
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373583
Filename
4242260
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