Title :
Monolithic multiplier/divider
Author_Institution :
Raytheon Co., Mountain View, CA, USA
Abstract :
A monolithic analog multiplier/divider circuit which achieves less than 0.03% FS nonlinearity error with a large signal bandwidth of 3MHz will be reported. Design also incorporates nonlinearity compensation.
Keywords :
Bandwidth; Bipolar transistors; Circuit synthesis; Costs; Differential amplifiers; Fabrication; Geometry; Nonlinear equations; Resistors; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1979.1155930
