DocumentCode :
2867286
Title :
A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation
Author :
Yoo, Kwisung ; Lee, Dongmyung ; Han, Gunhee ; Park, Sung Min ; Oh, Won Seok
Author_Institution :
Yonsei Univ., Seoul
fYear :
2007
fDate :
11-15 Feb. 2007
Firstpage :
56
Lastpage :
57
Abstract :
A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21psrms jitter for 231-1 PRBS, 9.5mVpp input sensitivity with BER <10-12, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm2.
Keywords :
CMOS integrated circuits; amplifiers; optical communication equipment; 0.18 micron; 1.2 V; 2.5 Gbit/s; 40 dB; 5.2 mW; CMOS technology; limiting amplifier; negative-impedance compensation; Active inductors; Bandwidth; CMOS technology; Circuits; High speed optical techniques; Optical amplifiers; Optical receivers; Optical sensors; Semiconductor optical amplifiers; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0852-0
Electronic_ISBN :
0193-6530
Type :
conf
DOI :
10.1109/ISSCC.2007.373585
Filename :
4242262
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2867286
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