DocumentCode :
2867334
Title :
LAGS System Using Data/Instruction Grain Power Control
Author :
Ikeda, Makoto ; Sogabe, Taku ; Ishii, Ken ; Mizuno, Masayuki ; Nakura, Toru ; Nose, Koichi ; Asada, Kunihiro
Author_Institution :
Tokyo Univ.
fYear :
2007
fDate :
11-15 Feb. 2007
Firstpage :
66
Lastpage :
587
Abstract :
A locally asynchronous, globally synchronous (LAGS) system with data/instruction grain control is presented for the optimization of power supply voltage, speed performance, PVT and noise tolerance. A LAGS CPU with on-chip DC-DC converter that occupies 250times60mum2 in 90nm CMOS has 0.98V to 0.68V VDD control with 50ns/85ns transition time and a speedtracing accuracy of 5%
Keywords :
CMOS integrated circuits; DC-DC power convertors; computer power supplies; power control; 0.68 to 0.98 V; 50 ns; 85 ns; 90 nm; CMOS technology; DC-DC converter; data-instruction grain power control; locally asynchronous globally synchronous system; noise tolerance; Central Processing Unit; Clocks; DC-DC power converters; Delay effects; Frequency synchronization; Power control; Power supplies; Pulse width modulation converters; Timing; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
Type :
conf
DOI :
10.1109/ISSCC.2007.373590
Filename :
4242267
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2867334
بازگشت