Interconnect strategies for deep submicron CMOS manufacture

As CMOS chips are scaled to deep submicron dimensions, interconnect strategy remains a key gateway for performance and manufacturability. ITRS´99 projections seriously underestimate the number of wiring levels required, even though inductance effects can significantly reduce wiring level requirements. By examining the requirements for a Multimedia Internet Processor, we project more reasonable wiring level requirements. The effects of alternative interconnect materials are considered, and the importance of appropriate interconnect strategies is emphasized