Evaluation of an advanced wafer carrier for ILD planarization

Author

Jaso, Mark ; Glynn, Thomas ; Giunta, Joesph ; Diefenderfer, David

Author_Institution

Dominion Semicond., Manassas, VA, USA

fYear

2000

fDate

2000

Firstpage

419

Lastpage

421

Abstract

The ground rule reduction of the dimensions used in semiconductor manufacturing has increased the number of yielding devices extending into the 3 mm edge exclusion area on the wafer. The use of a conventional topring for interlevel dielectric chemical-mechanical planarization was evaluated against an advanced topring. The advanced topring was designed to improve the post planarization film uniformity in the edge region. The use of the advanced topring for interlevel dielectric polishing was shown to improve the uniformity of polished films in this region. The improved film uniformity and edge profile resulted in increased device yield

Keywords

chemical mechanical polishing; dielectric thin films; chemical-mechanical planarization; device yield; edge profile; film uniformity; interlevel dielectric; polishing; semiconductor manufacturing; topring; wafer carrier; Chemical processes; Dielectrics; Fixtures; Measurement standards; Planarization; Plasma measurements; Semiconductor device manufacture; Semiconductor device modeling; Semiconductor films; Silicon compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

0-7803-5921-6

Type

conf

DOI

10.1109/ASMC.2000.902621

Filename

902621