• DocumentCode
    2867434
  • Title

    Testing a high density logic masterslice

  • Author

    Lowden, R.

  • Author_Institution
    IBM Corp., Hopwell Junction, NY, USA
  • Volume
    XXII
  • fYear
    1979
  • fDate
    14-16 Feb. 1979
  • Firstpage
    250
  • Lastpage
    251
  • Abstract
    Testing strategy for high density logic in a manufacturing environment will be covered. The approach is applicable to all wiring personalities of a T2L gate logic masterslice.
  • Keywords
    Circuit faults; Circuit testing; Driver circuits; Integrated circuit testing; Latches; Logic design; Logic testing; Sequential analysis; Test pattern generators; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1979.1155940
  • Filename
    1155940
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2867434