Design of the Power6 Microprocessor

Author

Friedrich, Joshua ; McCredie, Bradley ; James, Norman ; Huott, Bill ; Curran, Brian ; Fluhr, Eric ; Mittal, Gaurav ; Chan, Eddie ; Chan, Yuen ; Plass, Donald ; Chu, Sam ; Le, Hung ; Clark, Leo ; Ripley, John ; Taylor, Scott ; Dilullo, Jack ; Lanzerotti, M

Author_Institution

IBM Syst. Group, Austin, TX

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

96

Lastpage

97

Abstract

The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm² 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.

Keywords

integrated circuit design; integrated circuit interconnections; microprocessor chips; silicon-on-insulator; 65 nm; POWER6 microprocessor; SOI process; dual-core microprocessor; highly scalable memory subsystem; low-k copper interconnect; ultra-high frequency operation; Circuits; Clocks; Feedback; Frequency; Hardware; Latches; Logic arrays; Microprocessors; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373605

Filename

4242282