Title :
An 8-Core 64-Thread 64b Power-Efficient SPARC SoC
Author :
Nawathe, Umesh Gajanan ; Hassan, Mahmudul ; Warriner, Lynn ; Yen, King ; Upputuri, Bharat ; Greenhill, David ; Kumar, Ashok ; Park, Heechoul
Author_Institution :
SUN Microsystems, Sunnyvale, CA
Abstract :
The 8-core 64-thread 64b power-efficient 2nd-generation Niagara SPARC SoC has 4MB L2 cache with one times8 PCI-Express, two 10G Ethernet (XAUI), and 8 FBDIMM ports. The on-chip SerDes provide greater than 1Tb/s bandwidth. The 500M transistor chip with a die size of 342mm 2 is implemented in a 11M 65nm triple-Vt CMOS process
Keywords :
cache storage; integrated circuit design; logic design; low-power electronics; system-on-chip; 4 MBytes; 64 bit; 65 nm; CMOS process; Ethernet; FBDIMM ports; L2 cache; Niagara SPARC SoC; PCI-Express; on-chip SerDes; power-efficient SPARC SoC; system-on-chip; Aggregates; Clocks; Counting circuits; Cryptography; Delay; Ethernet networks; Microprocessors; Packaging; Power system reliability; Pulse generation;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373611
