DocumentCode :
28677
Title :
Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration
Author :
Morris, Randy W. ; Kodi, Avinash Karanth ; Louri, Ahmed ; Whaley, Ralph D.
Volume :
63
Issue :
1
fYear :
2014
fDate :
Jan. 2014
Firstpage :
243
Lastpage :
255
Abstract :
As throughput, scalability, and energy efficiency in network-on-chips (NoCs) are becoming critical, there is a growing impetus to explore emerging technologies for implementing NoCs in future multicore and many-core architectures. Two disruptive technologies on the horizon are nanophotonic interconnects (NIs) and 3D stacking. NIs can deliver high on-chip bandwidth while delivering low energy/bit, thereby providing a reasonable performance-per-watt in the future. Three-dimensional stacking can reduce the interconnect distance and increase the bandwidth density by incorporating multiple communication layers. In this paper, we propose an architecture that combines NIs and 3D stacking to design an energy-efficient and reconfigurable NoC. We quantitatively compare the hardware complexity of the proposed topology to other nanophotonic networks in terms of hop count, network diameter, radix, and photonic parameters. To maximize performance, we also propose an efficient reconfiguration algorithm that dynamically reallocates channel bandwidth by adapting to traffic fluctuations. For 64-core reconfigured network, our simulation results indicate that the execution time can be reduced up to 25 percent for Splash-2, PARSEC, and SPEC CPU2006 benchmarks. Moreover, for a 256-core version of the proposed architecture, our simulation results indicate a throughput improvement of more than 25 percent and energy savings of 23 percent on synthetic traffic when compared to competitive on-chip electrical and optical networks.
Keywords :
bandwidth allocation; multiprocessing systems; network-on-chip; 3D stacking; 64-core reconfigured network; PARSEC; SPEC CPU2006 benchmarks; Splash-2; channel bandwidth dynamic reallocation; competitive on-chip electrical networks; energy efficiency; energy-efficient NoC; hardware complexity; high on-chip bandwidth; interconnect distance reduction; many-core architectures; minimal reconfiguration; multicore architectures; multiple communication layers; nanophotonic interconnects; nanophotonic networks; optical networks; reconfigurable NoC; synthetic traffic; three-dimensional stacked nanophotonic network-on-chip architecture; Bandwidth; Energy efficiency; Network-on-chip; Optical device fabrication; Optical receivers; Optical ring resonators; Optical waveguides; 3D stacking; CMP; Nanophotonics; NoC; reconfigurable;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2012.183
Filename :
6256662
Link To Document :
بازگشت