DocumentCode
2867754
Title
Satisfying timing constraints of preemptive real-time tasks through task layout technique
Author
Datta, Anupam ; Choudhury, Sidharth ; Basu, Anupam ; Tomiyama, Hiroyuki ; Dutt, Nikil
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
fYear
2001
fDate
2001
Firstpage
97
Lastpage
102
Abstract
In multi-tasking preemptive real-time systems, a tighter estimate of the Worst Case Response Time (WCRT)s of the tasks can be obtained if the layout of the tasks is taken into account in the analysis. This is because the Cache Related Preemption Delay (CRPD) depends on the inter-task interference in the cache. We present an ILP formulation and an algorithm for generating a layout of the tasks such that the timing constraints of all the tasks are met. An attempt is made to generate a layout such that the CRPD is reduced for all the tasks. The performance of the proposed formulation is demonstrated
Keywords
cache storage; delay estimation; integer programming; linear programming; processor scheduling; real-time systems; timing; ILP formulation; algorithm; cache related preemption delay; inter-task interference; multi-tasking preemptive real-time systems; preemptive real-time tasks; task layout technique; timing constraints satisfaction; worst case response time; Computer science; Costs; Delay; Embedded computing; Equations; Interference; Linear approximation; Performance analysis; Real time systems; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2001. Fourteenth International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-7695-0831-6
Type
conf
DOI
10.1109/ICVD.2001.902646
Filename
902646
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