Analysis of a current sensing and reporting tolerance in an inductor DCR sense topology

This paper shows a method to design an inductor DCR sense circuit that achieves a tight tolerance and good sigma level across all the units in a high volume manufacturing environment. Ultimately, the problem that we are trying to solve is to help designers get rid of the large tolerance seen on the current sensed on many DCR sensed based circuits. The paper presents a novel way to derive the expression of the sensing capacitor voltage, taking into account the resonant circuit time constants mismatch. The expression obtained is shown to be more accurate than what was previously published in the literature. The paper presents a statistical method to compute the total error on the current drawn by a chip, reported to it by the VR controller. Experimental data obtained from a design done using the proposed statistical methods are also shown. The results are shown to yield an overall sigma level that is acceptable industry wide.