Title :
Implementation of read-k-times BDDs on top of standard BDD packages
Author :
Günther, Wolfgang ; Drechsler, Rolf
Author_Institution :
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
Abstract :
Ordered Binary Decision Diagrams (OBDDs) are the state-of-the-art data structure in VLSI CAD for representation and manipulation of Boolean functions. But due to the ordering restriction, many Boolean functions cannot be represented efficiently. As one alternative read-k-times BDDs have been proposed. They are a generalization of OBDDs in the way that variables may occur up to k times on each path, while they may only occur once in OBDDs. More functions can be represented by read-k-times BDDs in polynomial space than by OBDDs, while many operations, like synthesis and satisfiability, still have polynomial worst case behavior. In this paper, we present a new technique for implementation of read-k-times BDD packages on top of standard OBDD implementations. Thus, highly optimized OBDD packages can be used and only few changes in the code are needed, while the new type of decision diagram allows much smaller representations. Experimental results are given to demonstrate the efficiency of the approach
Keywords :
Boolean functions; VLSI; binary decision diagrams; circuit CAD; integrated circuit design; logic CAD; Boolean functions; VLSI CAD; data structure; highly optimized OBDD packages; ordered binary decision diagrams; ordering restriction; polynomial space; polynomial worst case behavior; read-k-times BDDs; satisfiability; standard BDD packages; synthesis; Binary decision diagrams; Boolean functions; Computer science; Data structures; Formal verification; Logic design; Packaging; Polynomials; Very large scale integration;
Conference_Titel :
VLSI Design, 2001. Fourteenth International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-7695-0831-6
DOI :
10.1109/ICVD.2001.902657