Title :
A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability
Author :
Kaeriyama, Shunichi ; Kajita, Mikihiro ; Mizuno, Masayuki
Author_Institution :
NEC, Sagamihara
Abstract :
A clock generator fabricated in 90nm CMOS occupies 300times128mum2 die area and dissipates 40mW at 1.2V. An interleaved clock-edge control technique extends the frequency tuning range and enables control of both rising and falling edge timing. A clock-period dithering technique enhances frequency tuning resolution. Disturbance-control functions that control jitter, duty cycle, and clock skew make timing margin testing possible
Keywords :
CMOS integrated circuits; clocks; timing; 1 to 2 GHz; 1.2 V; 40 mW; 90 nm; CMOS; clock skew; clock-period dithering; disturbance-control functions; duty cycle control; falling edge timing; interleaved clock-edge control; jitter control; on chip clock generator; rising edgae timing; timing margin testing; timing-margin test capability; Automatic control; Automatic testing; Circuit testing; Clocks; Frequency synchronization; Jitter; Logic testing; National electric code; Pulse generation; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373350
