DocumentCode :
2868331
Title :
Partitioning routing area into zones with distinct pins
Author :
Sinha, K. ; Sur-Kolay, S. ; Dasgupta, P.S. ; Bhattacharya, B.B.
Author_Institution :
Kalyani Eng. Coll., India
fYear :
2001
fDate :
2001
Firstpage :
345
Lastpage :
350
Abstract :
Topological routing has gained importance in state-of-the-art layout synthesis. This paper poses the problem of partitioning the routing area of a given placement into a minimum set of zones such that in each zone, no two pins belong to the same net. Thus, topological routing can be completed among the zones whereas within a zone the only wires are from a pin to the boundary of the zone. Hence, such partitioning may accelerate routing by reducing the problem size. The related problem of identifying a zone with maximum number of distinct pins is also considered here. Both problems are observed to be NP-hard. A genetic algorithm for the first one and a greedy heuristic for the second problem are proposed. Experimental results are observed to be near optimal in most of the cases
Keywords :
VLSI; circuit layout CAD; computational complexity; genetic algorithms; integrated circuit layout; network routing; network topology; NP-hard; genetic algorithm; greedy heuristic; problem size; routing area partitioning; state-of-the-art layout synthesis; topological routing; Acceleration; Educational institutions; Engineering management; Genetic algorithms; Integrated circuit interconnections; Pins; Routing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2001. Fourteenth International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
0-7695-0831-6
Type :
conf
DOI :
10.1109/ICVD.2001.902683
Filename :
902683
Link To Document :
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