Minimizing area and maximizing porosity for cell layouts using innovative routing strategies

This paper presents an enhanced maze routing algorithm to get a dense yet porous cell layout, which is electromigration and latch-up safe, for `tall cell´ (high performance) architectures. By placing ports at the most optimal location, discouraging routing between two ports and preventing vertical routes from blocking ports at the edge of the cell we ensure that the layout has minimum area and maximum routability. By encouraging power routing in diffusion and restricting use of metal near the power bus, we provide free tracks for through the cell routing by chip level router. By placing bulk contacts between shared diffusions and choosing proper well/substrate contacts, we prevent any latch-up problems. We also ensure that the nets carrying high drive currents are EM safe by routing them with wider (non-default) wires. These automation strategies enabled us to achieve production quality layout for around 80% of core cells of a high performance ASIC library. The result was minimization of layout generation time (as no manual intervention was necessary) leading to a faster ASIC library development cycle