Crosstalk noise verification in digital designs with interconnect process variations

Author

Nagaraj, N.S. ; Balsara, Poras ; Cantrell, Cyrus

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

2001

fDate

2001

Firstpage

365

Lastpage

370

Abstract

Interconnect parasitics are playing a significant role in design and analysis in deep sub-micron (DSM) technologies. Interconnect process variations could play a significant role in achieving predictable yield. Crosstalk noise is one of the increasingly important careabouts in DSM designs. In this paper, a practical method to analyze the crosstalk noise effects with interconnect process variations using corner-based approach is described. The results from application of this method on a large DSP design implemented in 0.18μ technology is presented. Application of the proposed method resulted in detection of a new worst case interconnect process corner that was not included in the design methodology

Keywords

VLSI; circuit CAD; crosstalk; digital signal processing chips; integrated circuit design; integrated circuit interconnections; integrated circuit noise; integrated circuit yield; logic CAD; 0.18 micron; DSM designs; corner-based approach; crosstalk noise verification; deep sub-micron technologies; design methodology; interconnect parasitics; interconnect process variations; large DSP design; predictable yield; worst case interconnect process corner; Circuit noise; Conducting materials; Crosstalk; Dielectrics; Digital signal processing; Frequency; Integrated circuit interconnections; Process design; Semiconductor device noise; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2001. Fourteenth International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-7695-0831-6

Type

conf

DOI

10.1109/ICVD.2001.902686

Filename

902686