Observability register architecture for efficient production test and debug of VLSI circuits

We present a simple design innovation and a testing methodology that overcomes the known difficulties in using linear feedback shift register based observability registers for failure isolation. The design makes diagnosing failures speedy and efficient during both the initial test development phase and the subsequent production and field failure analysis phase. The design architecture can be easily implemented on VLSI circuits, such as high-performance microprocessors, for enhancing the test effectiveness of at-speed functional tests. We present some results from its deployment on Compaq´s Alpha 21264 microprocessor