VLSI architectures for high-speed MAP decoders

Soft-in/soft-out building blocks are becoming increasingly important in present and future communication systems as they enable better communications performance. The maximum a posteriori (MAP) algorithm is the best known soft-in/soft-out decoder: its performance is superior to the soft-out Viterbi algorithm (SOVA). However optimized high-speed MAP decoder implementation is widely unexplored. We present a novel VLSI high-speed MAP architecture with optimized memory size and power consumption suitable for decoding the revolutionary “Turbo-Codes” and related concatenation schemes. The architecture is highly scalable with respect to throughput, expanding its applicability over a wide range of throughput requirements (300 Mbit/s-45 Gbit/s and above). An in-depth design space exploration on multiple abstraction levels has been carried out. Area and power consumption are significantly reduced compared to the state-of-the-art