Title :
A 1Mb full wafer MOS RAM
Author :
Egawa, Y. ; Tsuda, Naoaki ; Masuda, Kohji
Author_Institution :
NTT Musashino Electrical Communication Lab., Tokyo, Japan
Abstract :
Use of defect tolerant technologies, with a double-layer polysilicon gate structure applied to the output transistor directly connected to a bus line, will be described. Access time is 350 ns. Bit substitution is used for peripheral circuit failure, while 32-word block substitution is used for defects in storage units.
Keywords :
Circuits; MOSFETs; Protection; Read-write memory; Timing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1979.1156008
