DocumentCode :
2868625
Title :
A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver
Author :
Park, Matt ; Bulzacchelli, John ; Beakes, Michael ; Friedman, Daniel
Author_Institution :
Massachusetts Inst. of Technol., Cambridge, MA
fYear :
2007
fDate :
11-15 Feb. 2007
Firstpage :
230
Lastpage :
599
Abstract :
A 7Gb/s 2-tap current-integrating DFE implemented in a 90nm CMOS process is presented. Low power dissipation (9.3mW) is achieved by replacing resistively loaded analog current summers with resettable integrators. With 7Gb/s PRBS-7 data, the input sensitivity is 61 mVpp-diff, and the DFE equalizes a 16-inch backplane with 45% horizontal eye opening. The DFE core (integrators, latches, clock buffers) occupies 85 times 65mum2.
Keywords :
CMOS integrated circuits; decision feedback equalisers; receivers; 2-tap current-integrating DFE receiver; 9.3 mW; 90 nm; CMOS process; DFE core; low power dissipation; resettable integrators; CMOS technology; Capacitors; Circuits; Clocks; Decision feedback equalizers; Parasitic capacitance; Power dissipation; Prototypes; Switches; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
Type :
conf
DOI :
10.1109/ISSCC.2007.373378
Filename :
4242349
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2868625
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