Title :
A CMOS 1Gb/s 5-Tap Transversal Equalizer Based on Inductorless 3rd-Order Delay Cells
Author :
Hernandez-Garduno, David ; Silva-Martinez, Jose
Author_Institution :
Texas A & M Univ., College Station, TX
Abstract :
The 5-tap FIR structure uses 3rd-order linear-phase cells to implement delays of 500ps for a T/2 fractionally-spaced equalizer. To improve the bandwidth of the summing circuit, the design incorporates a transimpedance load, increasing the bandwidth by a factor of 3.6 over a conventional resistive load. The equalizer consumes 96mW with plusmn1.5V and occupies 0.26mm2 in a CMOS 0.35mum process.
Keywords :
CMOS integrated circuits; equalisers; summing circuits; 0.35 micron; 96 mW; CMOS 5-tap transversal equalizer; fractionally-spaced equalizer; inductorless 3rd-order delay cells; summing circuit; transimpedance load; Backplanes; Bandwidth; Delay lines; Energy consumption; Equalizers; Filters; Frequency; Inductors; Parasitic capacitance; Summing circuits;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373379
