• DocumentCode
    2868667
  • Title

    Cascading Techniques for a High-Speed Memory Interface

  • Author

    Gu, Zheng ; Gregorius, Peter ; Kehrer, Daniel ; Neumann, Lydia ; Neuscheler, Evelyn ; Rickes, Thomas ; Ruckerbauer, Hermann ; Schledz, Ralf ; Streibl, Martin ; Zielbauer, Juergen

  • Author_Institution
    Qimonda, Munich
  • fYear
    2007
  • fDate
    11-15 Feb. 2007
  • Firstpage
    234
  • Lastpage
    599
  • Abstract
    A memory interface operating up to 5.3Gb/s in a 70nm standard DRAM process is presented. The interface uses differential point-to-point signaling in a chain of 6 devices, in transparent- or resample-repeat mode. Transparent-repeat mode measurements at 4.8Gb/s show eye reduction of 8% Ul per device due to jitter accumulation. The last device in the repeat chain has an eye opening of 0.5UI at BER < 1012. The transparent-repeat mode consumes 40% less power and has 80% less latency than resample mode
  • Keywords
    DRAM chips; cascade systems; system buses; 5.3 Gbit/s; 70 nm; DRAM process; cascading techniques; differential point-to-point signaling; high-speed memory interface; transparent-repeat mode; Bit error rate; Circuits; Clocks; Jitter; Packaging; Performance gain; Random access memory; Repeaters; Sampling methods; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0853-9
  • Electronic_ISBN
    0193-6530
  • Type

    conf

  • DOI
    10.1109/ISSCC.2007.373380
  • Filename
    4242351
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2868667