Title :
A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOS
Author :
Hesener, M. ; Eichler, T. ; Hanneberg, A. ; Herbison, D. ; Kuttner, F. ; Wenske, H.
Author_Institution :
Infineon Technol., Munich
Abstract :
A 2-channel time-interleaved 40MS/s SAR ADC with redundancy is presented. The 0.13mum 1.5V CMOS design runs at 480MHz iteration clock and features 89dB THD and 81dB SNDR. Including the PLL, the second-order anti-alias filter, and reference buffer, the chip consumes 66mW and occupies 0.55mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; buffer circuits; clocks; filters; phase locked loops; redundancy; 0.13 micron; 1.5 V; 14 bit; 480 MHz; 66 mW; CMOS design; PLL; iteration clock; redundant SAR ADC; reference buffer; second-order anti-alias filter; time-interleaved SAR ADC; Capacitors; Clocks; Decoding; Degradation; Delay; Filters; Frequency; Multiplexing; Pipelines; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373387
