Title :
A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure
Author :
Agarwala, S. ; Rajagopal, A. ; Hill, Allyson ; Joshi, Madhura ; Mullinnix, S. ; Anderson, T. ; Damodaran, R. ; Nardini, L. ; Wiley, P. ; Groves, P. ; Apostol, J. ; Gill, Michael ; Flores, Jose ; Chachad, A. ; Hales, A. ; Chirca, Kai ; Panda, K. ; Venkatas
Author_Institution :
Texas Instruments, Dallas, TX
Abstract :
The combined processing power of three 1+GHz DSP cores and 65nm 7M CMOS integration delivers a WCDMA macro base-station on a single chip. The 300M transistor IC can perform up to 24000MIPS, 8000 16b MMACs per second, coupled with symbol-rate and chip-rate acceleration and dissipates less than 6W.
Keywords :
CMOS digital integrated circuits; UHF integrated circuits; code division multiple access; digital signal processing chips; 16 bit; 65 nm; 7M CMOS integration; C64x+ multicore DSP; WCDMA macro base-station; chip-rate acceleration; communications infrastructure; symbol-rate acceleration; Clocks; Delay; Digital signal processing; Digital signal processing chips; Libraries; Multiaccess communication; Protection; Random access memory; Read-write memory; Routing;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373394
