Title :
A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS
Author :
Ito, Masayuki ; Hattori, Toshihiro ; Irita, Takahiro ; Tatezawa, K. ; Tanaka, Fumihito ; Hirose, Kenji ; Yoshioka, Shinichi ; Ohno, Koji ; Tsuchihashi, Reiko ; Sakata, Minoru ; Yamamoto, Masayuki ; Aral, Y.
Author_Institution :
Renesas Technol., Tokyo
Abstract :
A single-chip 11.15times11.15mm2 application and dual-mode WCDMA/HSDPA and GSM/EDGE baseband processor achieves 390MHz in triple-V, low-power 90nm 8M CMOS. A CPU core standby mode with resume cache reduces leakage current of each CPU to 0.04mA when idle. A dynamic bus clock-stop scheme further reduces power consumption. Interconnect buffers allow the chip to support 30f/s VGA video.
Keywords :
CMOS integrated circuits; cellular radio; code division multiple access; leakage currents; low-power electronics; microprocessor chips; 0.04 mA; 390 MHz; 90 nm; CMOS technology; EDGE baseband processor; GSM baseband processor; HSDPA; WCDMA; bus clock-stop scheme; interconnect buffers; leakage current; Baseband; CMOS process; Cellular phones; Clocks; Control systems; Delay; Hardware; Logic circuits; Power dissipation; Read-write memory;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373400
