The use of VHDL for the whole design flow of digital radio devices

VHDL, the IEEE-standard hardware description language, is achieving popularity among digital electronics designers as an input for automatic synthesis tools, which are able to convert abstract descriptions into logic. However, VHDL can be used for much more ambitious tasks in the design process, and finds application throughout the whole design flow, including specification-VHDL was conceived to merely do so-, high-level simulation and evaluation of the complete system, even if analog blocks are involved, lower-level description of the digital devices for their automatic synthesis, and effortless documentation of the hardware designed. The paper presents a real-life VHDL design experience, as a means to discuss the pros and cons of this new methodology