DocumentCode
2869089
Title
A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications
Author
Chien, Chih-Da ; Lin, Chien-Chang ; Yi-Hung Shih ; Chen, He-Chun ; Huang, Chia-Jui ; Yu, Cheng-Yen ; Chen, Chih-Liang ; Cheng, Ching-Hwa ; Guo, Jiun-In
Author_Institution
National Chung-Cheng Univ., Chia-Yi
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
282
Lastpage
603
Abstract
A multi-standard (JPEG/MPEG-1/2/4/H.264) video decoder includes 252kgates and 4.9kB internal memory in a core size of 4.2times1.2mm 2 using 0.13mum 1P8M CMOS. The power consumption at 1.2V supply is 71 mW at 120MHz for real-time HD1080 and 7.9mW at 20MHz for real-time H.264 decoding of D1 video
Keywords
CMOS integrated circuits; high definition video; video codecs; video coding; 0.13 micron; 1.2 V; 120 MHz; 20 MHz; 4.9 kByte; 7.9 mW; 71 mW; CMOS technology; H.264 decoding; HD1080; JPEG; MPEG-1; MPEG-2; MPEG-4; high-definition video; video decoder; Bandwidth; CMOS technology; Clocks; Decoding; Delay; Energy consumption; Hardware; High definition video; Memory management; Size control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0853-9
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373404
Filename
4242375
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