Leveraging the Multiprocessing Capabilities of Modern Network Processors for Cryptographic Acceleration

Author

Gaubatz, G. ; Sunar, B.

Author_Institution

Cryptography & Inf. Security Lab., Worcester Polytech. Inst., MA

fYear

2005

fDate

27-29 July 2005

Firstpage

235

Lastpage

238

Abstract

The Kasumi block cipher provides integrity and confidentiality services for 3G wireless networks, but it also forms a bottleneck due to its computational overhead. Especially in infrastructure equipment with data streams from multiple connections entering and leaving the network processor the critical performance issue needs to be addressed. In this paper we present a highly scalable bit sliced implementation of the Kasumi block cipher for the Intel IXP 28xx family of network processors. It can achieve a maximum theoretical encryption rate of up to 2 Gb/s when run in parallel on all 16 on-chip microengines

Keywords

computer architecture; cryptography; microprocessor chips; network-on-chip; 16 on-chip microengine; Intel IXP 28xx family; cryptographic acceleration; encryption rate; highly scalable bit sliced Kasumi block cipher; multiprocessing capability; network processor; Acceleration; Clocks; Computer architecture; Computer networks; Cryptography; Data security; Engines; Random access memory; Read-write memory; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Network Computing and Applications, Fourth IEEE International Symposium on

Conference_Location

Cambridge, MA

Print_ISBN

0-7695-2326-9

Type

conf

DOI

10.1109/NCA.2005.28

Filename

1565960