• DocumentCode
    2869341
  • Title

    A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology

  • Author

    Gebara, F.H. ; Schaub, Jeremy D. ; Nguyen, Tuyet Y. ; Pena, Jarom ; Vo, Ivan ; Boerstler, David ; Nowka, K.J.

  • Author_Institution
    IBM, Austin, TX
  • fYear
    2007
  • fDate
    11-15 Feb. 2007
  • Firstpage
    312
  • Lastpage
    313
  • Abstract
    Two PLLs were designed using current-steering interpolating ring oscillators. The regular-V, PLL demonstrates a 3.2times lock range and a maximum frequency of 24.6GHz with 1.28psrms jitter at 1V. The high-V, PLL exhibits a 3.5times lock range at 6% lower frequency. The 0.18mm2 PLLs consume 16mW of power from 1V and are fabricated in a PD-SOI 65nm technology
  • Keywords
    clocks; oscillators; phase locked loops; silicon-on-insulator; 1 V; 16 mW; 18 GHz; 24.6 GHz; 65 nm; clock generator; phase locked loops; ring oscillators; silicon-on-insulator; Charge pumps; Circuits; Clocks; Filters; Frequency; Inverters; Jitter; Phase locked loops; Voltage; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0853-9
  • Electronic_ISBN
    0193-6530
  • Type

    conf

  • DOI
    10.1109/ISSCC.2007.373419
  • Filename
    4242390
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2869341