A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications

Author

Wang, Y. ; Ahn, H. ; Bhattacharya, U. ; Coan, T. ; Hamzaoglu, F. ; Hafez, W. ; Jan, C.-H. ; Kolar, P. ; Kulkarni, S. ; Lin, J. ; Ng, Y. ; Post, I. ; Wei, L. ; Zhang, Y. ; Zhang, K. ; Bohr, M.

Author_Institution

Intel, Hilisboro, OR

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

324

Lastpage

606

Abstract

A low-power high-speed SRAM macro is implemented in an ultra-low-power 8M 65nm CMOS for mobile applications. The 1Mb macro features a 0.667μm² low-leakage memory cell and operates with supply voltage from 0.5V to 1.2V. It operates at a frequency of 1.1 GHz at 1.2V and 250MHz at 0.7V. Leakage is reduced to 12μA/Mb at the data retention voltage of 0.5V. The measured bitcell leakage from the SRAM array is ~2pA/b at retention voltage with integrated leakage reduction schemes.

Keywords

CMOS memory circuits; SRAM chips; mobile computing; 0.5 to 1.2 V; 1.1 GHz; 250 MHz; 65 nm; 8M CMOS; SRAM design; integrated leakage reduction; low-leakage memory cell; mobile application; CMOS technology; Circuits; Dynamic voltage scaling; Energy consumption; Frequency; Leakage current; MOS devices; Random access memory; Subthreshold current; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0852-0

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373425

Filename

4242396