Author :
Yabuuchi, M. ; Nii, Koji ; Tsukamoto, Yuya ; Ohbayashi, Shigeki ; Imaoka, S. ; Makino, Hiroaki ; Yamagami, Yuuhei ; Ishikura, Satoshi ; Terano, Toshio ; Oashi, T. ; Hashimoto, Keiji ; Sebe, Akio ; Okazaki, Gen ; Satomi, Katsuji ; Akamatsu, Hironori ; Shin
Abstract :
A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum2 and 0.327mum2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.
Keywords :
CMOS memory circuits; SRAM chips; 45 nm; 512 kbyte; CMOS; embedded SRAM; passive resistance; process variation immunity; read assist; temperature variation immunity; variation-tolerant assist circuits; write assist; CMOS technology; Circuit simulation; Decoding; Degradation; Driver circuits; MOS devices; Random access memory; Rats; Temperature dependence; Voltage;
