A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

Author

Yabuuchi, M. ; Nii, Koji ; Tsukamoto, Yuya ; Ohbayashi, Shigeki ; Imaoka, S. ; Makino, Hiroaki ; Yamagami, Yuuhei ; Ishikura, Satoshi ; Terano, Toshio ; Oashi, T. ; Hashimoto, Keiji ; Sebe, Akio ; Okazaki, Gen ; Satomi, Katsuji ; Akamatsu, Hironori ; Shin

Author_Institution

Renesas Technol., Itami

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

326

Lastpage

606

Abstract

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided V_DD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum² and 0.327mum² are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.

Keywords

CMOS memory circuits; SRAM chips; 45 nm; 512 kbyte; CMOS; embedded SRAM; passive resistance; process variation immunity; read assist; temperature variation immunity; variation-tolerant assist circuits; write assist; CMOS technology; Circuit simulation; Decoding; Degradation; Driver circuits; MOS devices; Random access memory; Rats; Temperature dependence; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373426

Filename

4242397