DocumentCode :
2869743
Title :
A single 5V 64K dynamic RAM
Author :
Itoh, Kenji ; Hori, R. ; Masuda, Hiroji ; Kamigaki, Y. ; Kawamoto, Hiroaki ; Katto, H.
Author_Institution :
Hitachi Central Research Laboratory, Tokyo, Japan
Volume :
XXIII
fYear :
1980
fDate :
13-15 Feb. 1980
Firstpage :
228
Lastpage :
229
Abstract :
This paper will report on a single 5V, 64K dynamic RAM with a substrate-bias generator, typical power dissipation of 170mW at 300ns cycle time, access time of 120ns and 25.8mm2chip area.
Keywords :
Capacitance; Circuits; DRAM chips; Decoding; Inverters; Noise reduction; Signal to noise ratio; Surges; Switches; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location :
San Francisco, CA, USA
Type :
conf
DOI :
10.1109/ISSCC.1980.1156076
Filename :
1156076
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2869743
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