Title :
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor
Author :
Drake, Alan ; Senger, Robert ; Deogun, Harmander ; Carpenter, Gary ; Ghiasi, Soraya ; Nguyen, Tuyet ; James, Norman ; Floyd, Michael ; Pokala, Vikas
Author_Institution :
IBM, Austin, TX
Abstract :
A distributed critical-path timing monitor (CPM) is designed as part of the POWER6trade microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process variation, localized noise and VDD droop, or clock stability. It tracks critical-path delay to within 3 FO2 delays at extreme operating voltages with a standard deviation less than frac12 an FO2 delay. The CPM detects DC VDD droops greater than 10mV and tracks timing changes greater than 1 FO2 delay.
Keywords :
delay circuits; microprocessor chips; silicon-on-insulator; timing circuits; 65 nm; FO2 delay; POWER6 microprocessor; SOI; clock stability; critical-path delay; distributed critical-path timing monitor; high-performance microprocessor; Circuit synthesis; Clocks; Delay effects; Delay lines; Detectors; Microprocessors; Monitoring; Timing; Voltage; Wire;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373462
