• DocumentCode
    2870089
  • Title

    A One-Cycle Lock Time Slew-Rate-Controlled Output Driver

  • Author

    Kwak, Young-Ho ; Jung, Inhwa ; Lee, Hyung-Dong ; Choi, Young-Jung ; Yogendera Kumar ; Kim, Chulwoo

  • Author_Institution
    Korea Univ., Seoul
  • fYear
    2007
  • fDate
    11-15 Feb. 2007
  • Firstpage
    408
  • Lastpage
    611
  • Abstract
    A low-power output-on-demand slew-rate-controlled output driver is presented. It has an open-loop digital scheme and a one-cycle lock time applicable to high-speed memory interfaces. The output driver maintains slew rate between 2.1V/ns and 3.6V/ns for the SSTL interface. Fabricated in a 0.18mum CMOS process, the control block of the proposed driver occupies 0.009mm2 and consumes 13.7mW at 1Gb/s. No external resistance is needed to calibrate the output resistance of the output driver.
  • Keywords
    CMOS integrated circuits; driver circuits; 0.18 micron; 1 Gbit/s; 13.7 mW; CMOS process; high-speed memory interfaces; one-cycle lock time; open-loop digital scheme; slew-rate-controlled output driver; Clocks; Crosstalk; Delay; Detectors; Driver circuits; Inverters; Open loop systems; Phase locked loops; Signal generators; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0853-9
  • Electronic_ISBN
    0193-6530
  • Type

    conf

  • DOI
    10.1109/ISSCC.2007.373467
  • Filename
    4242438
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2870089