Title :
A Single-Cycle-Access 128-Entry Fully Associative TLB for Multi-Core Multi-Threaded Server-on-a-Chip
Author :
Shastry, Shashank ; Bhatia, Ajay ; Reddy, Sagar
Author_Institution :
Sun Microsystems, Sunnyvale, CA
Abstract :
A single-cycle-access, 128-entry fully-associative multi-context TLB was designed for the Niagara2 SPARCtrade processor in 65nm triple-V, 11M 1.1V CMOS. The circuit includes a dual-storage CAM cell, a modified dual matchline, an 8T 1-read/1-write based RAM, 4-way comparators for cache hit, a priority encoder, a multi-match detect, and data parity
Keywords :
CMOS integrated circuits; buffer circuits; cache storage; comparators (circuits); microprocessor chips; random-access storage; 1.1 V; 65 nm; CMOS process; RAM; cache hit; comparators; data parity; dual-storage CAM cell; fully-associative multicontext TLB; modified dual matchline; multicore multithreaded server-on-a-chip; multimatch detect; priority encoder; single-cycle-access TLB; CADCAM; Circuits; Clocks; Computer aided manufacturing; Flip-flops; MOS devices; Microprocessors; Random access memory; Read-write memory; Testing;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373468
