Title :
A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery
Author :
Harwood, Mike ; Warke, Nirmal ; Simpson, Richard ; Leslie, Tom ; Amerasekera, Ajith ; Batty, Sean ; Colman, Derek ; Carr, Eugenia ; Gopinathan, Venu ; Hubbins, Steve ; Hunt, Peter ; Joy, Andy ; Khandelwal, Pulkit ; Killips, Bob ; Krause, Thomas ; Lytollis
Author_Institution :
Texas Instruments, Northampton
Abstract :
A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of <10-15 is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm2 per TX/RX pair
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; clocks; data communication; equalisers; low-power electronics; radio receivers; telecommunication channels; 12.5 Gbit/s; 24 dB; 330 mW; 5-tap DFE; 65 nm; CMOS integrated circuits; DSP-based low-power SerDes; backplane data communication; baud-rate analog-to-digital converter; channel compensation; clock recovery; digital 2-tap FFE; digital RX equalization; digital data-path; legacy backplanes; Backplanes; Clocks; Decision feedback equalizers; Delay; Error-free operation; Finite impulse response filter; Intersymbol interference; Jitter; Phase locked loops; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373481
