Title :
Time interleaved converter arrays
Author :
Black, W. ; Hodges, D.A.
Author_Institution :
University of California, Berkeley, CA, USA
Abstract :
An A/D converter technique which uses an array of four 7b converters, with interleaved sampling intervals affording rates exceeding 2MHz, will be covered. A 10μ metal gate CMOS chip is used.
Keywords :
Bandwidth; CMOS process; Equations; Jitter; Linearity; Phased arrays; Sampling methods; Signal analysis; Signal sampling; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1980.1156111
