Title :
A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output
Author :
Masuda, Takashi ; Suzuki, Hideyuki ; Iizuka, Hiroshi ; Igarashi, Akiko ; Takeshita, Kaneyoshi ; Mogi, Takayuki ; Shoji, Norio ; Chatwin, Jeremy ; Butler, Iain ; Mellor, Derek
Author_Institution :
Sony, Tokyo
Abstract :
A full-rate 10 Gb/s transceiver core employing a tri-state binary PD with 100ps gated digital output is implemented in a 90nm CMOS process. Direct drive from the VCO is utilized to eliminate the 10GHz clock buffer current. The RX exhibits a recovered-clock jitter of 906fsrms and an input sensitivity of 5.9mVpp. The TX generates a jitter of 5mUIrms. The chip consumes 250mW.
Keywords :
CMOS integrated circuits; buffer circuits; clocks; jitter; radio receivers; transceivers; voltage-controlled oscillators; 10 GHz; 10 Gbit/s; 100 ps; 250 mW; 90 nm; CMOS process; clock buffer current; full-rate transceiver core; tri-state binary PD; voltage controlled oscillator; Bandwidth; Clocks; Frequency; Impedance; Jitter; Logic; Parasitic capacitance; Transceivers; Transmitters; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373482
