• DocumentCode
    2870472
  • Title

    A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS

  • Author

    Jeon, Young-Deuk ; Lee, Seung-Chul ; Kim, Kwi-Dong ; Kwon, Jong-Kee ; Kim, Jongdae

  • Author_Institution
    Electron. & Telecommun. Res. Inst., Daejeon
  • fYear
    2007
  • fDate
    11-15 Feb. 2007
  • Firstpage
    456
  • Lastpage
    615
  • Abstract
    A 4.7mW 10b 30MS/s pipelined ADC is implemented without a front-end S/H for low power consumption and small area. The prototype ADC, fabricated in a 90nm CMOS process, shows an SNDR of 58.4dB and an SFDR of 75.2dB with a 2MHz sinusoidal input sampled at 30MS/S. The 0.32 mm2 chip dissipates 4.7mW at a 1V supply and has a FOM of 0.23pJ/conversion-step.
  • Keywords
    CMOS digital integrated circuits; analogue-digital conversion; 1 V; 10 bit; 2 MHz; 4.7 mW; 90 nm; CMOS process; pipelined analog-to-digital converter; Apertures; Band pass filters; Capacitors; Circuits; Energy consumption; Frequency measurement; Prototypes; Sampling methods; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0853-9
  • Electronic_ISBN
    0193-6530
  • Type

    conf

  • DOI
    10.1109/ISSCC.2007.373491
  • Filename
    4242462
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2870472