DocumentCode :
2870516
Title :
A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS
Author :
Hernes, BjØrnar ; BjØrnsen, Johnny ; Andersen, Terje N. ; Vinje, Anders ; Korsvoll, Håvard ; TelstØ, Frode ; Briskemyr, Altle ; HoldØ, Christian ; Moldsvor, Øystein
Author_Institution :
Nordic Semicond., Trondheim
fYear :
2007
fDate :
11-15 Feb. 2007
Firstpage :
462
Lastpage :
615
Abstract :
A 10b 205MS/S IF sampling pipelined ADC is fabricated in 1.2/3.3V 0.13μm CMOS. Power consumption and die area are improved by using single-stage opamps throughout the pipeline chain; digital calibration compensates for the reduced stage gain. Foreground calibration is used to shorten the start-up time and background calibration is used afterwards. The ADC has ENOB of 9.0, ERBW of 330MHz, dissipates 92.5mW, and occupies 0.52mm2.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; operational amplifiers; 0.13 micron; 1.2 V; 10 bit; 3.3 V; 330 MHz; 92.5 mW; CMOS integrated circuits; IF sampling; digital calibration; operational amplifiers; pipeline chain; pipelined IF analog-to-digital converter; single-stage opamps; Calibration; Capacitors; Clocks; Feedback loop; Frequency; Nonlinear distortion; Pipelines; Sampling methods; Switches; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0852-0
Electronic_ISBN :
0193-6530
Type :
conf
DOI :
10.1109/ISSCC.2007.373494
Filename :
4242465
Link To Document :
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