Title :
MOS buried load logic
Author :
Sakai, Yoshiki ; Masuhara, T. ; Minato, O. ; Hashimoto, Noriaki
Author_Institution :
Hitachi Central Research Laboratory, Tokyo, Japan
Abstract :
A MOS buried logic technique using buried JFET loads with a gate delay of 0.34ns and a power delay product of 0.17pJ will be reported. Development has been applied to a 4-stage binary counter operating with a maximum toggle of 72.4MHz.
Keywords :
CMOS technology; Counting circuits; Delay; Electron devices; Frequency; Inverters; Logic; Physics; Power dissipation; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1980.1156123
