2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read

Author

Kawahara, T. ; Takemura, R. ; Miura, K. ; Hayakawa, J. ; Ikeda, S. ; Lee, Y. ; Sasaki, R. ; Goto, Y. ; Ito, K. ; Meguro, T. ; Matsukura, F. ; Takahashi, H. ; Matsuoka, H. ; Ohno, H.

Author_Institution

Hitachi, Tokyo

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

480

Lastpage

617

Abstract

A 1.8V 2Mb spin-transfer torque RAM chip using a 0.2mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power non-volatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bidirectional current write to achieve proper spin-transfer torque writing in 100ns, and parallelizing-direction current reading with a low-voltage bit-line that leads to 40ns access time.

Keywords

logic circuits; low-power electronics; magnesium compounds; random-access storage; tunnelling; 0.2 micron; 1.8 V; 100 ns; 2 Mbit; 40 ns; MgO; bit-by-bit bidirectional current write; logic process; low-power nonvolatile RAM; parallelizing-direction current read; spin-transfer torque RAM; tunneling barrier cell; universal memory; Driver circuits; Latches; Magnetic tunneling; Nonvolatile memory; Random access memory; Read-write memory; Switches; Switching circuits; Torque; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373503

Filename

4242474