A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier

Author

Barth, John ; Reohr, William ; Parries, Paul ; Fredeman, Greg ; Golz, John ; Schuster, Stanley ; Matick, Richard ; Hunter, Hillery ; Tanner, C. ; Harig, Joseph ; Kim, Hoki ; Khan, Babar ; Griesemer, John ; Havreluk, Robert ; Yanagisawa, Kenji ; Kirihata,

Author_Institution

IBM, Burlington, VT

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

486

Lastpage

617

Abstract

A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces performance-enhancing 3T micro sense amplifier architecture (muSA). The macro was characterized via a test chip fabricated in a 65nm SOI deep-trench DRAM process. Measurements confirm 1.5ns random access time with a 1V supply at 85deg and low voltage operation with a 600mV supply.

Keywords

DRAM chips; amplifiers; low-power electronics; microprocessor chips; silicon-on-insulator; 1 V; 1.5 ns; 500 MHz; 600 mV; 65 nm; SOI deep-trench DRAM process; SOI embedded DRAM; high-performance microprocessors; low voltage operation; microsense amplifier; Application specific integrated circuits; Degradation; Feedback; Logic; MOS devices; Microprocessors; Random access memory; Silicon on insulator technology; Timing; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373506

Filename

4242477